The EEPROM (Electrically Erasable Programmable Read-Only Memory) structure based on the SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) transistor has the following requirements as shown in Table 1 for the gate voltage of the memory cell, i.e., the wordline voltage WLS, and for the substrate VBULK of the memory cell:
TABLE 1Unselected wordIn the sameIn the sameIn the differentcolumn butrow butrow andSelecteddifferentdifferentdifferentwordrowcolumncolumnWLSErasingVNEGVPOSVSSVSSProgrammingVPOSVNEGVSSVSSVBULKErasingVPOSVPOSVSSVSSProgrammingVNEGVNEGVSSVSS
Wherein VPOS is the erasing positive voltage, a positive high voltage required for erasing and programming, and VNEG is the erasing negative voltage, a negative high voltage required for erasing and programming. While programming, the gate and the substrate of the selected memory cell are applied with VPOS and VNEG, respectively, and carry out the programming operation; both the gate and the substrate of the unselected memory cell in the same column with the selected memory cell are applied with VNEG, and the programming operation will not be carried out. While erasing, the gate and the substrate of the selected memory cell are applied with VNEG and VPOS, respectively, the erasing operation will be carried out; both the gate and the substrate of the unselected memory cell in the same column with the selected memory cell are applied with VPOS, the programming operation will not be carried out. VSS represents ground.
As shown in FIG. 1, an existing EEPROM memory cell gate control signal generating circuit comprises: its generating circuit is divided into two parts: a high-voltage row decoding circuit 101 and a plurality of word selection circuits, such as a word selection circuit 1 and a word selection circuit n, which are marked with 1021 and 102n, respectively, wherein 102i represents any word selection circuit i, with i being any digit from 1 to n.
The total wordline voltage GWLS is generated by the high-voltage row decoding circuit 101. The total wordline voltage GWLS needs the two values, VNEG and VPOS, wherein VPOS is generated by the PMOS transistors P0 and P1 under the control of the control signals X2SP, S2SPB, OE_SP and VDP, and VNEG is generated by the NMOS transistors N0 and N1 under the control of the control signals X2SN, S2SNB, OE_SN and VDN. However, the drains of the PMOS transistors P0 and P1 cannot be connected directly to the drains of the NMOS transistors N0 and N1; otherwise, when the drains of the PMOS transistors P0 and P1 output VPOS, VNEG will appear at the gates of the NMOS transistors N0 and N1, which will make the voltage of the gate oxide layer of the NMOS transistors N0 and N1 too high; when the drains of the NMOS transistors N0 and N1 output VNEG, VPOS will appear at the gates of the PMOS transistors P0 or P1, which will make the voltage of the gate oxide layer of the PMOS transistors P0 or P1 too high. Therefore, a PMOS transistor P2 and an NMOS transistor N2 need to be added to the existing technology to realize isolation, wherein the gate of the PMOS transistor P2 is connected to the ground VSS, and the gate of the NMOS transistor N2 is connected to the working voltage VDD, which make the voltage of the gate oxide layer of the PMOS transistors P0 and P1 and the NMOS transistors N0 and N1 reduced, thus protecting the gate oxide layer.
The word selection circuit is the same in structure. Taking i of any digit from 1 to n as an example, the word selection circuit i includes the PMOS transistor 4i, and the NMOS transistors N4i, N6i and N5i, with the individual grids connected to the control signals BSPBi, BSNi, VDD and BDN, respectively; the word selection circuit i outputs the wordline voltage WSLi, which selects an output from the total wordline voltage GWLS and VSS, with the total wordline voltage GWLS including the two voltages, VPOS and VNEG. Likewise, the PMOS transistor P3i is used for protection of the gate oxide layer of the PMOS transistor P4i, and the NMOS transistor N3i is used for protection of the gate oxide layer of the NMOS transistor N4i, the gate of the PMOS transistor P3i being connected to the ground VSS, the gate of the NMOS transistor N4i being connected to the working voltage VDD.